Design of a QPSK Signal Source Based on FPGA

Phase modulation pulse signal can obtain a large compression ratio. As a commonly used pulse compression signal, it has been widely used in modern radar and communication systems. With the development of software radio technology and electronic technology in recent years, DDS (Direct Digital Frequency Synthesis) is becoming more and more widely used for signal generation. DDS technology performs frequency synthesis based on the concept of phase. It uses digital sampling and storage technology to generate various forms of signals such as point frequency, linear frequency modulation, ASK, PSK and FSK. It has good amplitude and phase consistency and simple circuit control. The advantages of phase accuracy, high frequency resolution, fast frequency switching, low phase noise of the output signal, and easy realization of full digital design.

At present, DDS ASIC chips, such as the AD9852 and AD9854 of AD, can easily generate BPSK for phase-modulated signals. However, it is difficult to implement QPSK or 8PSK. They require extremely high control update pulses once the deviation exceeds DDS. The internal system clock is extremely high and the output phase is wrong. This paper introduces a method to realize QPSK or higher order PSK signal through FPGA. It can flexibly control the parameters through the PCI bus of the host computer to generate QPSK with different carrier frequency, different pulse width, different duty cycle and different repetition periods. Signals have a good reference for designers of radar and other systems.

DDS is a fully digital frequency synthesizer consisting of a phase accumulator, a sinusoidal waveform ROM memory, a D/A converter and a low-pass filter. The basic principle is shown in Figure 1.

The frequency of the output signal is fout=fclk·Δφ/2N, and the minimum frequency resolution is Δfo=fomin=fo/2N. It can be seen that changing the frequency control word N can change the frequency of the output signal. When the reference clock frequency is given, the frequency of the output signal depends on the control word of the frequency. The frequency resolution depends on the number of bits of the accumulator. The phase resolution depends on the number of address lines of the ROM. The amplitude quantization depends on the data word of the ROM. The number of bits in the long and D/A converter.

In order to improve the spectral index of the DDS output signal and reduce the sinusoidal ROM memory, recent developments such as adding digital inverse sinc filtering after phase truncation, using trigonometric symmetry to access only 1/4 cycle lookup table, based on CORDIC, Taylor series Techniques such as weighted frequency synthesis methods.

QPSK signal source design

In the FPGA, DDS is realized by a sine lookup table and a phase accumulator, and the start and stop control of the QPSK signal is realized by a counter. When the counter counts to zero, the flag is set and the QPSK control code in the register is read to set the initial phase. After counting the value set according to the QPSK pulse width, the counter is set to 0 and restarts counting. After the number and number of set symbols have been run, the output disable flag is enabled.

The repetition period of the QPSK signal is also implemented by a counter. Set the number of bits in the counter and make it meet the requirements based on the range of the cycle and the system clock. After the counter counts to the set value, the flag of the output disable is cleared. It should be noted that the cycle counter should be synchronized with the QPSK symbol width counter.

The QPSK signal parameter control is implemented by the PCI bus, including the start and end of the QPSK signal, the number of symbols, the number of times, the code word, and the QPSK signal repetition period. Read and save parameters in the FPGA through registers.

The FPGA uses XC3S1000 from Spartan3 series of XILINX Company, which is a large-scale programmable device of 1 million gates. It has a 432kbit Block Ram and a 120kbit Distributed Ram; four clock management units DCM; 24 multipliers. The configuration uses XILINX's dedicated PROM XCF04S, 4M bit serial flash PROM. The XC3S1000 implements the main string configuration through XCF04S, and M0, M1, and M2 are both set low. The system block diagram is shown in Figure 2.

The high-speed DAC uses AD's AD9767, which is a dual-channel, 14-bit precision, high-speed CMOS DAC. It integrates a 1.2V voltage reference, SFDR and IMR up to 83dBc, the highest conversion rate is 125MSPS, and the full-scale current is adjustable from 2mA to 20mA. The two D/A outputs are amplified by two high-speed, wideband amplifiers AD8047. Then through the filter output, the AD8047 gain is 1 to achieve current to voltage conversion.

The PCI interface chip adopts PCI9054, which is a 32-bit, 33MHz PCI bridge chip widely used by PlX, which realizes the conversion between PCI bus and local bus. PCI9054 can work in master and slave modes, support DMA, and support burst operations. The PCI9054 is powered up via a 2k-bit EEPROM NM93CS56, including the PCI9054's local bus control and PCI configuration space register configuration. PCI9054 should pay attention to the length constraint of PCI bus and clock in PCB design.

In order to increase the storage capacity on the board, the FPGA has been extended by CYPRESS's CY7C1372C-200 (512k & TImes; 36) / 1M & TImes; 18-bit ZBT SRAM. The read/write rate is up to 200MHz with zero wait state, and the maximum access time is 3ns. It supports Burst operation and is suitable for high-speed data reading and writing.

The system uses an external SMA clock, and the internal 50MHz crystal oscillator is output via the clock buffer chip CY2308, which is used as the local clock of PCI9054 and FPGA respectively. The input impedance of the external clock is 50Ω. Note that the clock should be supplied from the signal source with a peak-to-peak value of 2V or more.

The reset circuit is implemented by MAXIM's watchdog and voltage monitoring chip MAX708.

The power supply is provided by the PCI bus. The 3.3V voltage is directly drawn from the 3.3V of the PCI bus. The 2.5V voltage is realized by the LT1764 of Linear Technology. The voltage of 1.2V is realized by TI's TPS54612, which is used as the auxiliary voltage of the FPGA Vccaux and the nuclear voltage Vccint. . TPS54612 input voltage is 3-6V, can be used in 3.3V, 5V, the output can be up to 6A, and the switch controller integrates FET FET inside, which is convenient for application. The positive and negative voltage inputs of the AD8047 are +5V and -5V, respectively, supplied by the +12V and -12V voltages from the PCI bus via regulators 7805 and 7905.

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