Pull-up resistor selection technique for i2c bus circuit

I2C (Inter-Intergrated Circuit) bus is a bus standard commonly used in the field of microelectronic communication control. It has the advantages of less wiring, simple control method and high communication speed.

The internal structure of the I2C bus is shown in Figure 1. The I2C device connected to the bus output stage must be in the form of open collector or open-drain to achieve the logic of the line AND. When the output terminal is not connected to the pull-up resistor, it can only output a low level. The output of the I2C bus must be connected to the pull-up resistor.

The pull-up resistors commonly found in I2C circuits are 1K, 1.5K, 2.2K, 3.3K, 4.7K, 5.1K, 10K, etc., but which one is more suitable?

Figure 1 I2C bus internal structure

The I2C specification defines a voltage below VIL or below 0.3VDD as a logic low, and also defines a voltage above VIH or above 0.7VDD as a logic high, as shown in Figure 2.

Figure 2 specifies the voltage levels of logic high and logic low

The supply voltage limits the minimum pull-up resistor value that allows the bus to be pulled low. Excessive pull-ups prevent the device from pulling down the pull-down level sufficiently, which prevents a logic low level from being detected. Specify the minimum pull-up resistor formula for I_OL to 3mA at the output stage V_OLmax=0.4V, allowing the bus voltage to be pulled low:

The functional relationship between V_DD and Rp is shown in Figure 3, respectively.

Figure 3 The minimum value of Rp is a function of voltage

Since the high level of the output of the port is realized by the pull-up resistor, when the level of the line changes from low to high, the power supply charges the line load capacitor CL through the pull-up resistor, which takes a certain time, that is, the rise time. The maximum value of the pull-up resistor is determined by the bus margin load. The bus load diagram is shown in Figure 4.

Figure 4 bus load structure diagram

Bus capacitance is mainly caused by factors such as pins, connections, PCB traces and wires. The bus capacitor and pull-up resistor R have an RC time constant, which becomes more and more important as the I2C communication rate increases. The general formula for charging a capacitor through a resistor:

rearrange,

Then we can calculate the time T1 when the voltage rises to VIL, the time T2 that rises to VHL, and the time TR between two levels, as shown in Figure 5. Since both VIL and VHL are V_DD generated, this formula is independent of the supply voltage and the V_DD term has been cancelled.

Figure 5 bus level rise time

Solve,

In I2C standard mode, the maximum load tolerance of 100Kbps bus is less than or equal to 400pF; in fast mode, the maximum load tolerance of 400Kbps bus is less than or equal to 200pF, the rise time of I2C bus is faster in fast mode, and the bus pull-up resistor is smaller than standard mode. The design is based on the fast mode 50Pf~200pF. The relationship between the maximum Rp value and the bus capacitance from (6) above is shown in Figure 6.

Figure 6 Rp maximum value in accordance with the fast mode I2C bus TRmax requirement is a function of bus capacitance

From the above calculations, it can be concluded that the pull-up resistor RP can take a range of 1.53K~7K @VDD = 5V, generally taking 5.1K, integrated into the 3.3V VDD low-power design, usually using 4.7K sacrificial speed for battery use. Time, this resistance is also a conventional resistance.

Regarding the pull-up resistor of I2C, the best way is to look at the reference design given by the official. If the trace is long or there are many slaves on the bus, the resistance will be reduced accordingly. If the reference design is not within the calculation range. Choose a conventional resistance value. In fact, we did not have to measure the bus capacitance problem, and only pay attention to the options and wiring.