January 09, 2025

Create ZYNQ processor design and use of Logic Analyzer

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Our goal is to create a Zynq Soc processor design and use the Logic Analyzer to debug the signals we are interested in.

First, open Vivado and create a project.

Create ZYNQ processor design and use of Logic Analyzer

Add these IP cores,

Create ZYNQ processor design and use of Logic Analyzer

Click Run ConnecTIon AutomaTIon to let the software automatically connect us. Select ALL AutomaTIon in the dialog that opens.

Create ZYNQ processor design and use of Logic Analyzer


Create ZYNQ processor design and use of Logic Analyzer

Ok, the software is automatically connected,

Create ZYNQ processor design and use of Logic Analyzer

If you want to observe the signal of interest, right click here - Generate Output Products, Create HDL Wrapper, compile, after the execution is complete, select the signal of interest, right-Mark,

Create ZYNQ processor design and use of Logic Analyzer

Then there will be changes in the block block diagram, as shown in the figure, two insects,

Create ZYNQ processor design and use of Logic Analyzer

Execute Set Up Debug, the signal just marked will appear.

Create ZYNQ processor design and use of Logic Analyzer

Next, set the sampling depth,

Create ZYNQ processor design and use of Logic Analyzer

Then execute Implement Design and Generate Bitstream. Export to SDK after completion.

Create ZYNQ processor design and use of Logic Analyzer


Create ZYNQ processor design and use of Logic Analyzer

To be continued. . .

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