However, FPGAs are not a panacea. Compared to serial architecture processors, the flexibility of their design is at the expense of increased workload. FPGA and ARM, DSP (as shown below) are compared below. First, from the point of view of differences in language itself, there is still a large gap between the Verilog HDL and VHDL-based hardware languages ​​and C/C++ in code flexibility and development efficiency. Usually when a dozen or more lines of C code are implemented using a hardware language, the amount of code increases to as many as tens of lines. At the same time, in the description of hardware language, a qualified FPGA engineer must not only implement the corresponding logic function, but also emerge in the mind the logic structure generated by the written code, and take into account the impact of the gate delay on the system timing. In this way, a stable and efficient logic structure can be designed to reduce post-timing adjustment work. Secondly, from the point of view of resource allocation, ARM, DSP and other processors integrate computing units, storage units, and a large number of bus interfaces. Engineers can make the bus interface work in the appropriate mode by correctly configuring each register parameter. The internal FPGA is a large number of logic resources, and the bus interface needs to be designed according to needs. There are only some special modules inside the FPGA, such as PLL and DSP units. Because in a system built by FPGA, many interfaces need to be designed by themselves, so it takes a lot of time for developers. Thirdly, from the view of operating frequency, ARM, DSP and other processors adopt a mature kernel structure and have better timing characteristics. The highest frequency is usually 600 MHz to 1.25 GHz. In order to improve processing capabilities, TI and other chip makers adopt a multi-core design method and have designed 8-core DSP and 8-core ARM processors. The maximum operating frequency of each core is 1.25 GHz. The cores can be turned on and off by setting them. To flexibly coordinate the conflict between power consumption and processing power. At present, TI is designing a processor with an 8-core ARM+8-core DSP to meet the needs of centralized computing in high-speed systems. In FPGA design, different systems have different maximum operating frequencies, which can be obtained in the compilation report. For Altera's FPGAs, adjusting the timing through TImeQuest tools can increase the maximum frequency of design engineering. A well-designed FPGA project can have a maximum frequency of more than 150 MHz. Fourth, from the perspective of execution mode, the C/C++ language based on the embedded platform is executed in the existing hardware structure, and only the relevant registers can be properly configured. The use of hardware language design needs to design its own hardware structure, before the generation of the structure but also through the former simulation, integration, layout and routing, post-simulation and other steps, the development cycle is longer. This situation is particularly serious in more complex FPGA engineering designs. For example, a project that adds 4 DDR2 IPs has a compile time of more than 20 minutes on i5 processors and 4G memory computers. Fifth, judging from the application of algorithms, processors such as adders and multipliers are integrated in processors such as ARM and DSP. Especially in DSPs, 8&TImes; 8-bit or even 16×16-bit multiplication can be performed in one cycle. Operation. At the same time, these processors also support floating-point computing capabilities. The FPGA is not good at this part of the operation, even in the simple addition operation, if the two data to be added have a higher bit width, because the conventional way of addition is a serial structure, it is generated in The structure will produce a longer gate delay, which will reduce the timing margin, and even reduce the maximum operating frequency after the system is compiled. Sixth, from the point of view of algorithm design, before designing algorithms in processors such as ARM and DSP, it is necessary to design the flow chart of the algorithm in advance, and then write the code. In FPGA design, there are mainly three design methods: state-oriented design, activity-oriented design, and structure-oriented design. Wireless Earphones,Wireless Earbuds,Wireless Earphones With Mic,Wireless Bluetooth Earphones Guangzhou YISON Electron Technology Co., Limited , https://www.yisonearphone.com