Automatic target recognition (ATR) algorithms typically include algorithms that automatically detect, track, identify, and select attack points. The complexity of the battlefield environment and the ever-increasing target type make the ATR algorithm more and more computational. Therefore, the ATR algorithm puts forward higher requirements on the processing power of the microprocessor. Since the general-purpose digital signal processing chip can realize various complicated operations through programming, high processing precision, large flexibility, small size, low power consumption, and high speed, the DSP chip is generally selected as a microprocessor to implement ATR. The engineering and practical application of the algorithm. In order to ensure real-time implementation of the ATR algorithm on the DSP processor, algorithm parallelization techniques are used. The three elements of algorithm parallelization processing are: 1 parallel architecture; 2 parallel software system; 3 parallel algorithm. Parallel architecture is the hardware foundation for algorithm parallelization, and parallel algorithms are parallel programs developed for specific parallel architectures. According to the number of DSP processors, the parallel implementation of the ATR algorithm can be divided into inter-processor parallel and intra-processor parallel. Parallel interprocessor refers to a multiprocessor parallel system in which multiple DSP processors are connected in some way. The ATR algorithm enters in parallel on multiple processors. Depending on the processor's use of memory, multiprocessor parallel systems can be further divided into shared memory multiprocessor parallel systems and distributed multiprocessor parallel systems. In-processor parallelism refers to the parallelization of the ATR algorithm through instruction-level parallelism (ILP) of multiple functional units within a single DSP processor. This paper discusses the parallel implementation of ATR algorithm on shared memory multiprocessor parallel system, distributed multiprocessor parallel system and instruction level parallel DSP processor. 1 Implement ATR algorithm on shared memory multiprocessing parallel system In a shared memory multiprocessor parallel system, each processor operates on all of the memories through a shared bus to implement data communication between the various processors. At any one time, only one processor is allowed to operate on the shared bus. Therefore, when the processor performs a read/write operation on the memory, it must first obtain control of the shared bus, which is implemented by a bus arbitration circuit. However, since all processors can only access the memory through a shared bus, it is easy to cause bus collision and wait and reduce the running speed of the entire parallel system when the number of processors is relatively large or data is frequently exchanged between processors. . The advantage of a shared memory multiprocessor parallel system is that the structure is simple, and when the number of processors is small, a higher speedup ratio can be achieved. The ADSP2106x processor supports the most commonly used shared memory multiprocessor parallel system. The on-chip memory of each ADSP2106x that makes up a multiprocessor system is uniformly addressed. Any ADSP2106x can access any other ADSP2106x on-chip memory. Since the on-chip SRAM is a dual-port memory, this access does not interrupt the normal operation of the accessed processor. Each processor's on-chip SRAM is both the local memory of the processor and part of the shared memory. The maximum number of processors directly connected through the external bus interface is six without increasing the auxiliary capacitance. Since each processor's work program is placed in its on-chip dual-port SRAM, each processor can implement parallel processing, which is determined by the memory structure of the ADSP2106x. When the ATR algorithm is implemented in a shared memory multiprocessor parallel system, the issues that should be considered in writing parallel algorithm programs include: (1) Balance tasks to individual processors The ATR algorithm implements task-level parallelism in a shared-memory multiprocessor parallel system. Therefore, the ATR algorithm must be divided into multiple tasks with computational load balancing, and each task is assigned to multiple processors to maximize the multiprocessor parallel system. Parallel efficiency. (2) Minimize data communication between multiple processors Since multiple processors can only access the memory through a shared bus, this can easily cause bus competition and reduce the running speed of the entire parallel system in the case of frequent data exchange between multiple processors. (3) Using parallel programming features of a single processor The full application of the parallel programming features of a single processor helps to reduce the running time of tasks on each processor. For example, the 32-bit floating-point unit of the ADSP2106x contains a multiplier, an adder, and a shift logic that work in parallel; bit-reversed addressing is useful in Fourier transform operations; circular addressing is used for convolution, digital filtering It is often used in operations. Nantong Boxin Electronic Technology Co., Ltd. , https://www.bosencontrols.com