Compared with the parallel bus, the serial bus has the advantages of simple structure, less occupied pins, and low cost. Common serial buses are USB, IEEE1394, I2C, etc. Among them, the I2C bus has the characteristics of simple use, and has a wide range of applications in single-chip computers, serial E2PROM, LCD and other devices. I2C (Inter IC BUS) is a bus developed by Philips for connection between chips. The I2C bus uses two signal lines for data transmission, one for the serial data line (SDA) and the other for the serial clock line (SCL). The I2C bus allows several compatible devices (such as memory, A / D converter, D / A converter, LCD driver, etc.) to share the bus. The maximum number of devices that the I2C bus can theoretically allow is based on the total capacitance of all devices on the bus (including the capacitance of the connection itself and the lead-out capacitor of the connection) not exceeding 400pF. All devices on the bus rely on the address sent by the SDA line Signal addressing does not require chip select lines. The bus can only be controlled by one master device at any time, and each slave device starts data transmission when the bus is idle. The standard mode rate of I2C bus data transmission is 100kbps, the fast mode rate is 400kbps, and the high-speed mode rate is 3.4Mbps. Designing digital systems with VHDL and CPLD has unparalleled advantages over traditional methods, and it has become the most effective means for large-scale integrated circuit design. For simplicity, this article uses VHDL to design a standard mode I2C bus control circuit. 1 Data transmission on I2C bus The I2C bus includes two connections, the clock line SCL and the data line SDA, and the SCL is generated by the host. The data transmission process of the I2C bus is shown in Figure 1. The transmission process is: first the host generates the start bit, and then transmits the first byte. Among the 8-bit data, the most significant bit is the MSB of the data, the lowest bit LSB is the read and write indicator bit, 1 means the host reads, 0 means the host writes, and the high 7-bit address allows the host to address 128 slave devices. The slave sends the response bit after receiving the first byte of data, and the master sends the second byte of data after receiving the response bit. After the data is sent, an end bit is generated and the data transfer is completed. During data transfer, SDA is allowed to switch only when the clock SCL is low, and SDA must be stable when SCL is high. At this time, the level of SDA is the value transferred by the bus. When SCL is high, the SDA line switches from high to low to indicate the start bit, and the SDA line switches from low to high to indicate the stop bit. The start bit and the stop bit are generated by the host. After the start bit is generated, the bus is in a busy state. The stop bit appears and the bus enters the idle state after a certain period of time. After each byte is sent by the transmitter, the receiver must generate a response bit. The drive clock for the response bit is generated by the host and the receiver pulls the SDA line low to generate the response bit. If the master is a receiver, when the last byte is received, the response bit is 1 to notify the slave to finish sending, otherwise the response bit is 0. When the slave cannot respond to the slave address (for example, it is executing some real-time functions and cannot receive or send), or responds to the slave address but cannot receive more data bytes after a period of transmission, the slave can The host is notified to terminate the current transmission by the response bit being 1, so the host generates a stop bit to terminate the transmission, or generates a repeated start bit to start a new transmission. The data transmitted on the SDA line must be 8 bits, and the number of bytes that can be sent per transmission is not limited. If the slave has to complete some other functions (such as executing an internal interrupt service routine) to receive or send the next data byte, the slave can maintain the SCL low, forcing the master to enter a wait state. When the slave is ready to receive or send the next data byte, the SCL is released and the data transmission continues. Both SDA and SCL are bidirectional lines and are connected to the power supply through pull-up resistors when in use. When the bus is idle, both lines are high. The output stage of the device connected to the bus must be open-drain or open-collector, so that the bus can perform the function of "AND AND". After the host sends the first byte, there may be three situations in which the data transmission direction changes. (1) The transmission direction remains unchanged, such as the host writing to the slave; (2) The transmission direction changes, such as the host reading data from the slave; (3) The transmission direction changes multiple times, such as the host reading and writing to the slave multiple times. 2 Clock synchronization and arbitration The I2C bus can only have one host at any time. When two or more devices on the I2C bus want to be the host at the same time, arbitration is required; the purpose of clock synchronization is to provide a definite clock for arbitration. Synchronization and arbitration of the clock SCL are performed by "AND AND". The low time of SCL depends on the host with the longest low time, and the high time depends on the host with the shortest high time. The arbitration process takes place on the SDA line of the data line. When SCL is high, if a host on the SDA line sends a low level, the host sending a high level will turn off the output stage. Because the state of the bus is different from itself, the host sending the low level wins arbitration. Arbitration can last for multiple bits. In the actual communication process, the first stage of arbitration compares address bits. If multiple masters address the same slave, continue to compare data bits (master is the transmitter) or response bits (master is Receiver). Since the address and data on the I2C bus are determined by the host that wins the bus, no information is lost during the arbitration process. If a master has the slave function, when it loses arbitration, it must immediately switch to the slave state, because it may be being addressed by another master.
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